EP2063328A2 - Electronic circuit for managing the operation of peripheral elements of a watch - Google Patents

Electronic circuit for managing the operation of peripheral elements of a watch Download PDF

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Publication number
EP2063328A2
EP2063328A2 EP08169910A EP08169910A EP2063328A2 EP 2063328 A2 EP2063328 A2 EP 2063328A2 EP 08169910 A EP08169910 A EP 08169910A EP 08169910 A EP08169910 A EP 08169910A EP 2063328 A2 EP2063328 A2 EP 2063328A2
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EP
European Patent Office
Prior art keywords
processor
electronic circuit
watch
circuit according
peripheral controllers
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Granted
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EP08169910A
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German (de)
French (fr)
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EP2063328A3 (en
EP2063328B1 (en
Inventor
Yves Godat
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EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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Priority to EP08169910.0A priority Critical patent/EP2063328B1/en
Publication of EP2063328A2 publication Critical patent/EP2063328A2/en
Publication of EP2063328A3 publication Critical patent/EP2063328A3/en
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Publication of EP2063328B1 publication Critical patent/EP2063328B1/en
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    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G21/00Input or output devices integrated in time-pieces
    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G19/00Electric power supply circuits specially adapted for use in electronic time-pieces

Definitions

  • the present invention generally relates to an electronic circuit for managing the operation of a watch having several functions. These functions are performed by different devices, each of these devices being controlled by a controller.
  • the electronic circuit comprises a processor connected to a non-volatile memory that contains instructions to be made, peripheral controllers for interacting with watch peripherals, and connection means arranged to allow peripheral controllers to the non-volatile memory and the processor communicating information relating to the operation of said watch, with each other.
  • the electronic circuits for managing this watch, that is to say for example to count the seconds, to rotate the hands or to manage the manual action of the user on the buttons of said watch.
  • the electronic circuits according to the prior art comprise a processor associated with a non-volatile memory storing program lines necessary for the operation of the watch, as well as peripheral controllers. These device controllers are responsible for making the connection between the devices of the watch such as the motor / needle assembly, the chain of division or others.
  • connection means for the transfer of information are arranged so that all communications pass through said processor.
  • each watch circuit is specifically wired according to the functions it has. This entails significant inventory risks of electronic watch circuits in the event that they have not had the expected success.
  • the invention relates to an electronic watch circuit which overcomes the aforementioned drawbacks of the prior art, namely large consumptions and a lack of flexibility, said circuit being intended to execute operations independently of the processor and / or the memory nonvolatile.
  • the invention relates to an electronic circuit for managing the operation of a watch cited above, which is characterized in that further includes initialization means that can act on the device controllers to initialize them and enable them to perform operations independently of the processor and / or the nonvolatile memory.
  • An advantage of the circuit according to the invention is that an initialization means is able to act on the peripheral controllers to initialize them and enable them to execute operations independently of the processor and / or the non-volatile memory. This ensures that on the one hand, it is possible for the peripherals to be autonomous with respect to the processor with or without the non-volatile memory without closing the door to a reintegration of said processor in the management of the operation of the watch. On the other hand, this allows a reduction of the power consumption which would go from 7.6 ⁇ A during a management according to the prior art to a consumption of the order of 400nA in the case of management according to the present invention.
  • Another advantage of the present invention is to guarantee a flexibility of the electronic watch circuit so that according to the present invention, the number of applications in the circuit is not fixed. This allows a series of manufacturing to another, less worry about inventory problems since the circuit is flexible enough to implement applications other than the original ones and therefore use this circuit in many products.
  • the present invention also relates to a method for initializing an electronic watch circuit so that the latter can be managed without the processor and the non-volatile memory where the code lines coding the applications are stored, are put into operation. .
  • this method is characterized in that an access to the initialization means is performed, then a reading of the data therein is made for then executed which allows the initialization of the controllers of peripherals.
  • a particular step of the process is the subject of the dependent claim 12.
  • the figure 1 schematically represents the electronic watch circuit 1 according to the present invention.
  • This circuit 1 manages the operation of a watch and comprises in the same chip, a processor 2 communicating with a non-volatile memory 3, peripheral controllers 4 communicating outside the electronic circuit 1 with the peripherals of the watch and communicating with the receiver.
  • internal circuit itself via connecting means 6a, 6b and 7.
  • These connecting means 6a, 6b and 7 allow peripheral controllers to communicate with each other but also with the processor 2 and therefore also with the non-volatile memory 3.
  • the electronic circuit 1 is powered by a voltage source, typically a battery, whose voltage is preferably 1.55V although a voltage other than this may be used. Of course, other power supply means are possible.
  • a voltage source typically a battery, whose voltage is preferably 1.55V although a voltage other than this may be used.
  • other power supply means are possible.
  • the technology used for it may be a nonvolatile memory technology 3 allowing the realization of a nonvolatile memory 3 of Flash or EEPROM type.
  • These non-volatile memories 3 allow rewriting of the data in the case of partial or total reprogramming according to the evolution of the electronic watch circuit 1 in time.
  • nonvolatile memories can be used.
  • the choice of one type of memory compared to another is based on characteristics of size, capacity, power consumption see access performance and reading of each type of memory considered.
  • This non-volatile memory 3 is intended to contain lines of codes of the instructions used for the operation of the watch. These instructions can be divided into two categories: standard instructions and specific instructions. Standard instructions are those instructions of the watch that are most commonly used or that are permanently integrated into electronic watch systems. For example, instructions for incrementing the time, displaying the time, the date or even the chronograph functions. Conversely, specific instructions are those instructions which are not necessary for the proper functioning of the watch or which are not all the time implanted in watches such as the instructions for managing a transceiver, instructions for use. external sensor controls, meteorological function management instructions, etc. Preferably, it is arranged for the non-volatile memory 3 to be consists of two distinct areas: a first where the standard instructions are written and a second where the specific instructions are written.
  • peripheral designation is given for the systems of the watch which are useful for the operation of said watch and the realization of the functions that the latter proposes.
  • the quartz accompanied by its division chain for timing the different elements.
  • the present circuit 1 comprises a single oscillator for clocking all the elements of the watch.
  • Other devices may be the motor systems of the hands or the display screen depending on whether it is an analog watch or digital.
  • the inputs / outputs that is to say the different buttons of the watch
  • optional peripherals can be the engine systems of a chronograph or the management systems of any function using a sensor like a compass or altimeter or whatever.
  • Each device is thus connected to a peripheral controller 4 located in said electronic watch circuit 1.
  • controllers each include an initialization register 5 for setting certain internal data to each peripheral such as, for example, the characteristics of the driving pulses: frequency , length or other in the case of the device controller of the driving pulse generator.
  • the different elements of the electronic circuit 1 are connected to each other via the connecting means 6a, 6b and 7. These are represented on the figure 1 partly by 2 multiplexers 6a and 6b. These multiplexers 6a and 6b are called initialization multiplexer 6a for the one which serves above all to allow initialization of the initialization registers 5 of the peripheral controllers 4, and the operating multiplexer 6b, for the one which serves for its part. allow the flow of data between the different elements when the circuit 1 is in normal operation.
  • the two multiplexers 6a and 6b are connected to the different elements by communication buses 7.
  • the processor 2 which is also capable of communicating with the 4. This is because the circuit 1 may optionally be independent of processor 2 and nonvolatile memory 3. It will also be pointed out that other connection means 6a, 6b and 7 may be used in the electronic watch circuit 1 according to the present invention.
  • the present circuit 1 differs from what is currently known by the presence of an initialization means 8 for configuring the peripheral controllers 4 and the connecting means 6a, 6b and 7 that is say the multiplexers 6a and 6b, so that the peripherals can operate completely independently of the processor 2 and the non-volatile memory 3.
  • This initialization means 8 is represented on the figure 1 as a programmable memory 8 containing the initialization data to be implemented in the initialization registers 5 of the peripheral controllers 4 and the initialization data of the connecting means 6a and 6b.
  • This programmable memory 8 is connected to the initialization registers 5 of the peripheral controllers 4 via the initialization multiplexer 6a and a communication bus 7.
  • This initialization means 8, the peripheral controllers 4 and the connection means 6a, 6b and 7 form the autonomous assembly 9 used for the watch to operate without intervention of the processor 2 and the non-volatile memory 3.
  • the initialization instructions that are set in the boot registers 5 of the peripheral controllers 4 are the following data. As data implanted in the various initialization registers, we first find the specific characteristics of the devices such as those mentioned before, these not contributing to the decrease in the power consumption of circuit 1, that is to say, not contributing to make the peripherals autonomous. The problem is solved by the implementation of instructions configuring the inputs / outputs of each device controller 4.
  • each device controller 4 has a series of inputs / outputs allowing it on the one hand to communicate with the device that corresponds to it, that is to say to receive information from the latter and other part to communicate with the processor 2, that is to say to transmit information to the processor 2 and to receive the data of the latter to be transmitted to the device.
  • the processor 2 that is to say to transmit information to the processor 2 and to receive the data of the latter to be transmitted to the device.
  • the processor 2 will process this information, that is to say, interpret what this change of state means and act accordingly, that is to say execute the instruction that manages the chronograph and transmit it to the corresponding peripherals, namely the chronograph and chronograph hands and motor as well as the clock.
  • the present invention differs from the prior art in that, in the case of the example above, the change of state of the actuated button variable will be sent directly to the peripherals so that they can fulfill their purpose. function.
  • the processor 2 which on the one hand, allows us to save time of cycles and on the other hand, allows us to gain in consumption since n There is no need to turn on processor 2 to perform these tasks.
  • the electronic watch circuit 1 had the possibility of using the processor 2 in order to execute specific instructions. But it should be noted that the processor 2 can also be turned on to execute standard instructions if necessary. Therefore, we will explain below the process so that the processor 2 is used for the purpose of executing these instructions.
  • the processor 2 must be able to be reset at any time as soon as an instruction that it is specific or standard, must be executed by said processor 2. For this, it is expected that each device can be able to send an interruption signal via the connection means 6a, 6b and 7 to the processor 2.
  • This interrupt signal enables the operation of the processor 2 so that to execute the instructions stored in the nonvolatile memory 3. To do this, the interrupt signal, once received by the processor 2, will trigger the awakening of the latter, which will then go from a passive mode to a active mode where he can perform tasks.
  • the processor 2 will access the non-volatile memory, read the corresponding instruction and then execute it, once this instruction has been executed, the processor 2 will be able to switch from an active mode to a passive mode in order to reduce the overall power consumption of the electronic watch circuit 1.
  • this embodiment where an interruption signal is used to allow the execution of instructions by the processor 2, is used for the execution of specific instructions.

Abstract

The circuit (1) has a processor (2) i.e. CPU, connected to a non-volatile memory (3) e.g. flash memory. Connection units constituted by multiplexers (6a, 6b) and a communication bus (7) connect peripheral controllers (4), the processor and the memory to communicate information relating to operation of a watch with each other. An initialization unit (8) i.e. programmable memory, acts on the controllers to initialize the controllers by sending data without intervention of the processor and by permitting the controllers to execute operations independent of the processor and the memory. An independent claim is also included for method for actuating an electronic circuit of a watch.

Description

La présente invention concerne de manière générale un circuit électronique pour la gestion du fonctionnement d'une montre ayant plusieurs fonctions. Ces fonctions sont exécutées par différents périphériques, chacun de ces périphériques étant piloté par un contrôleur. Le circuit électronique comprend un processeur relié à une mémoire non volatile qui contient des instructions à réaliser, des contrôleurs de périphériques pour interagir avec des périphériques de la montre, et des moyens de liaison agencés pour permettre aux contrôleurs de périphériques, à la mémoire non volatile et au processeur de communiquer des informations relatives au fonctionnement de ladite montre, les uns avec les autres.The present invention generally relates to an electronic circuit for managing the operation of a watch having several functions. These functions are performed by different devices, each of these devices being controlled by a controller. The electronic circuit comprises a processor connected to a non-volatile memory that contains instructions to be made, peripheral controllers for interacting with watch peripherals, and connection means arranged to allow peripheral controllers to the non-volatile memory and the processor communicating information relating to the operation of said watch, with each other.

ARRIERE PLAN TECHNOLOGIQUEBACKGROUND TECHNOLOGY

Il est connu dans l'art antérieur des circuits électroniques de montre permettant de gérer cette montre, c'est-à-dire par exemple de compter les secondes, de faire tourner les aiguilles ou de gérer l'action manuelle de l'utilisateur sur les boutons de ladite montre. Les circuits électroniques selon l'art antérieur comprennent un processeur associé à une mémoire non volatile stockant des lignes de programme nécessaires au fonctionnement de la montre, ainsi que des contrôleurs de périphériques. Ces contrôleurs de périphériques s'occupent de faire le lien entre les périphériques de la montre comme par exemple l'ensemble moteur/aiguilles, la chaîne de division ou autres.It is known in the prior art electronic watch circuits for managing this watch, that is to say for example to count the seconds, to rotate the hands or to manage the manual action of the user on the buttons of said watch. The electronic circuits according to the prior art comprise a processor associated with a non-volatile memory storing program lines necessary for the operation of the watch, as well as peripheral controllers. These device controllers are responsible for making the connection between the devices of the watch such as the motor / needle assembly, the chain of division or others.

La gestion d'une montre dans ce type de circuit électronique est totalement sous le contrôle du processeur par qui toutes les communications entre les différents éléments se font. Un exemple, dans le cas d'une mise en fonction du chronographe par l'utilisateur, en actionnant le bouton adéquat, cet appui va provoquer un changement d'état du signal correspondant. Ce changement d'état parvient au processeur qui va ensuite traiter cette information pour ensuite accéder à la mémoire, chercher l'instruction correspondante et l'exécuter en ordonnant aux périphériques concernés d'agir en adéquation avec cette instruction.The management of a watch in this type of electronic circuit is totally under the control of the processor by whom all communications between the different elements are done. An example, in the case of a start of the chronograph by the user, by pressing the appropriate button, this support will cause a change of state of the corresponding signal. This change of state reaches the processor which will then process this information to then access the memory, seek the corresponding instruction and execute it by ordering the relevant devices to act in adequacy with this instruction.

Une telle gestion pose néanmoins un certain nombre de problèmes dans le domaine de l'horlogerie. En effet, une des préoccupations majeures de l'industrie horlogère est d'augmenter la durée de vie de la pile d'une montre électronique. Or une gestion selon l'art antérieur implique que le processeur est très souvent en fonctionnement. Par exemple, rien que pour l'affichage de l'heure, le processeur doit se mettre en fonctionnement toutes les secondes afin d'incrémenter le temps et d'en opérer le changement sur le système d'affichage. Cela implique donc forcément une consommation électrique non négligeable réduisant par là, la durée de vie de la pile.Such management nevertheless raises a certain number of problems in the field of watchmaking. Indeed, one of the major concerns of the watch industry is to increase the life of the battery of an electronic watch. However management according to the prior art implies that the processor is very often in operation. For example, just for the display of the time, the processor must be running every second to increment the time and make the change on the display system. This necessarily implies a significant power consumption thereby reducing the life of the battery.

Un autre problème de cette gestion vient du fait que les moyens de liaison permettant le transfert des informations, sont agencés de sorte que toutes les communications passent par ledit processeur. Ainsi chaque circuit de montre est spécifiquement câblé selon les fonctions qu'il possède. Ceci entraîne des risques de stocks importants de circuits électroniques de montre dans le cas où ceux-ci n'auraient pas eu le succès escompté.Another problem of this management comes from the fact that the connection means for the transfer of information, are arranged so that all communications pass through said processor. Thus each watch circuit is specifically wired according to the functions it has. This entails significant inventory risks of electronic watch circuits in the event that they have not had the expected success.

RESUME DE L'INVENTIONSUMMARY OF THE INVENTION

L'invention concerne un circuit électronique de montre qui pallie les inconvénients susmentionnés de l'art antérieur à savoir d'importantes consommations et un manque de flexibilité, ledit circuit ayant pour but d'exécuter des opérations indépendamment du processeur et/ou de la mémoire non volatile.The invention relates to an electronic watch circuit which overcomes the aforementioned drawbacks of the prior art, namely large consumptions and a lack of flexibility, said circuit being intended to execute operations independently of the processor and / or the memory nonvolatile.

A cet effet, l'invention concerne un circuit électronique de gestion du fonctionnement d'une montre cité ci-devant, qui se caractérise en ce qu'il comprend en outre un moyen d'initialisation susceptible d'agir sur les contrôleurs de périphériques pour les initialiser et leur permettre d'exécuter des opérations indépendamment du processeur et/ou de la mémoire non volatile.For this purpose, the invention relates to an electronic circuit for managing the operation of a watch cited above, which is characterized in that further includes initialization means that can act on the device controllers to initialize them and enable them to perform operations independently of the processor and / or the nonvolatile memory.

Des modes de réalisation avantageux du circuit électronique font l'objet des revendications dépendantes 2 à 10.Advantageous embodiments of the electronic circuit are the subject of dependent claims 2 to 10.

Un avantage du circuit selon l'invention est qu'un moyen d'initialisation est susceptible d'agir sur les contrôleurs de périphériques pour les initialiser et leur permettre d'exécuter des opérations indépendamment du processeur et/ou de la mémoire non volatile. Ceci assure que d'une part, il est possible pour les périphériques d'être autonomes par rapport au processeur accompagné ou non de la mémoire non volatile sans pour autant fermer la porte à une réintégration dudit processeur dans la gestion du fonctionnement de la montre. D'autre part, cela permet une réduction de la consommation électrique qui passerait de 7.6µA lors d'une gestion selon l'art antérieur à une consommation de l'ordre de 400nA dans le cas d'une gestion selon la présente invention.An advantage of the circuit according to the invention is that an initialization means is able to act on the peripheral controllers to initialize them and enable them to execute operations independently of the processor and / or the non-volatile memory. This ensures that on the one hand, it is possible for the peripherals to be autonomous with respect to the processor with or without the non-volatile memory without closing the door to a reintegration of said processor in the management of the operation of the watch. On the other hand, this allows a reduction of the power consumption which would go from 7.6 μA during a management according to the prior art to a consumption of the order of 400nA in the case of management according to the present invention.

Enfin, un autre avantage de la présente invention est de garantir une flexibilité du circuit électronique de montre de sorte que selon la présente invention, le nombre d'applications dans le circuit n'est pas figé. Cela permet donc d'une série de fabrication à une autre, de moins se soucier des problèmes de stocks puisque le circuit est suffisamment flexible pour y implanter des applications autres que celles de départ et donc d'utiliser ce circuit dans de nombreux produits.Finally, another advantage of the present invention is to guarantee a flexibility of the electronic watch circuit so that according to the present invention, the number of applications in the circuit is not fixed. This allows a series of manufacturing to another, less worry about inventory problems since the circuit is flexible enough to implement applications other than the original ones and therefore use this circuit in many products.

La présente invention concerne également un procédé permettant l'initialisation d'un circuit électronique de montre afin que ce dernier puisse être géré sans que le processeur et la mémoire non volatile où sont stockées les lignes de codes codant les applications, ne soient mis en fonctionnement.The present invention also relates to a method for initializing an electronic watch circuit so that the latter can be managed without the processor and the non-volatile memory where the code lines coding the applications are stored, are put into operation. .

A cet effet, ce procédé se caractérise en ce qu'un accès au moyen d'initialisation est effectué, puis une lecture des données s'y trouvant est faite pour ensuite les exécutées ce qui permet l'initialisation des contrôleurs de périphériques.For this purpose, this method is characterized in that an access to the initialization means is performed, then a reading of the data therein is made for then executed which allows the initialization of the controllers of peripherals.

L'avantage de ce procédé venant du fait qu'il n'y a que les moyens d'initialisation à modifier selon les applications que l'on désire implanter dans la montre.The advantage of this method comes from the fact that there is only the initialization means to be modified according to the applications that one wishes to implant in the watch.

Une étape particulière du procédé fait l'objet de la revendication dépendante 12.A particular step of the process is the subject of the dependent claim 12.

BREVE DESCRIPTION DES FIGURESBRIEF DESCRIPTION OF THE FIGURES

Les buts, avantages et caractéristiques du circuit électronique de montre et de son procédé de mise en action apparaitront plus clairement dans la description détaillée suivante d'au moins une forme de réalisation de l'invention donnée uniquement à titre d'exemple non limitative et illustrée par le dessin annexé sur lequel :

  • la figure 1 représente de manière schématique le circuit électronique de montre selon la présente invention.
The purposes, advantages and characteristics of the electronic watch circuit and its actuation method will appear more clearly in the following detailed description of at least one embodiment of the invention given solely by way of nonlimiting example and illustrated. by the appended drawing in which:
  • the figure 1 schematically represents the electronic watch circuit according to the present invention.

DESCRIPTION DETAILLEE DE L'INVENTIONDETAILED DESCRIPTION OF THE INVENTION

Dans la description suivante, toutes les parties du circuit électronique qui sont bien connues d'un homme du métier dans ce domaine technique ne seront expliquées que de manière simplifiée. Ledit circuit électronique est principalement destiné au fonctionnement d'éléments ou périphériques de la montre.In the following description, all the parts of the electronic circuit which are well known to a person skilled in the art in this technical field will be explained only in a simplified manner. Said electronic circuit is mainly intended for the operation of elements or peripherals of the watch.

La figure 1 représente de manière schématique le circuit électronique de montre 1 selon la présente invention. Ce circuit 1 gère le fonctionnement d'une montre et comprend dans la même puce, un processeur 2 communiquant avec une mémoire non volatile 3, des contrôleurs de périphériques 4 communiquant en dehors du circuit électronique 1 avec les périphériques de la montre et communiquant avec l'intérieur même du circuit via des moyens de liaison 6a, 6b et 7. Ces moyens de liaison 6a, 6b et 7 permettent aux contrôleurs périphériques de communiquer entre eux mais aussi avec le processeur 2 et de ce fait, également avec la mémoire non volatile 3.The figure 1 schematically represents the electronic watch circuit 1 according to the present invention. This circuit 1 manages the operation of a watch and comprises in the same chip, a processor 2 communicating with a non-volatile memory 3, peripheral controllers 4 communicating outside the electronic circuit 1 with the peripherals of the watch and communicating with the receiver. internal circuit itself via connecting means 6a, 6b and 7. These connecting means 6a, 6b and 7 allow peripheral controllers to communicate with each other but also with the processor 2 and therefore also with the non-volatile memory 3.

Le circuit électronique 1 est alimenté par une source de tension, typiquement une pile, dont la tension est de préférence de 1.55V bien qu'une tension autre que celle-ci peut être utilisée. Bien sûr, d'autres moyens d'alimentation électrique sont envisageables.The electronic circuit 1 is powered by a voltage source, typically a battery, whose voltage is preferably 1.55V although a voltage other than this may be used. Of course, other power supply means are possible.

Concernant la mémoire non volatile 3, la technologie utilisée pour celle-ci, peut être une technologie de mémoire non volatile 3 permettant la réalisation d'une mémoire non volatile 3 de type Flash ou EEPROM. Ces mémoires non volatiles 3 permettent une réécriture des données dans le cas d'une reprogrammation partielle ou totale suivant l'évolution du circuit électronique de montre 1 dans le temps.Regarding the nonvolatile memory 3, the technology used for it may be a nonvolatile memory technology 3 allowing the realization of a nonvolatile memory 3 of Flash or EEPROM type. These non-volatile memories 3 allow rewriting of the data in the case of partial or total reprogramming according to the evolution of the electronic watch circuit 1 in time.

Néanmoins, tous les types de mémoires non volatiles peuvent être utilisés. Le choix d'un type de mémoire par rapport à un autre se fait en fonction de caractéristiques d'encombrement, de capacité, de consommation électrique voir de performances d'accès et de lecture de chaque type de mémoire envisagé.Nevertheless, all types of nonvolatile memories can be used. The choice of one type of memory compared to another is based on characteristics of size, capacity, power consumption see access performance and reading of each type of memory considered.

Cette mémoire non volatile 3 est destinée à contenir des lignes de codes des instructions utilisées pour le fonctionnement de la montre. Ces instructions peuvent être rangées en deux catégories : les instructions standards et les instructions spécifiques. On appelle instructions standards, les instructions de la montre qui sont les plus couramment utilisées ou qui sont en permanence intégrées dans les systèmes électroniques de montre. On pourra citer par exemple les instructions d'incrémentation de l'heure, d'affichage de l'heure, de la date ou même les fonctions de chronographe. A l'inverse, on appelle instructions spécifiques, les instructions qui ne sont pas nécessaires au fonctionnement propre de la montre ou qui ne sont pas tout le temps implantées dans les montres telles que les instructions de gestion d'un émetteur-récepteur, instructions de commandes d'un capteur externe, instructions de gestion de fonctions météorologiques, etc. Préférentiellement, on s'arrange pour que la mémoire non volatile 3 soit constituée de deux zones distinctes: une première où sont écrites les instructions standards et une seconde où sont écrites les instructions spécifiques.This non-volatile memory 3 is intended to contain lines of codes of the instructions used for the operation of the watch. These instructions can be divided into two categories: standard instructions and specific instructions. Standard instructions are those instructions of the watch that are most commonly used or that are permanently integrated into electronic watch systems. For example, instructions for incrementing the time, displaying the time, the date or even the chronograph functions. Conversely, specific instructions are those instructions which are not necessary for the proper functioning of the watch or which are not all the time implanted in watches such as the instructions for managing a transceiver, instructions for use. external sensor controls, meteorological function management instructions, etc. Preferably, it is arranged for the non-volatile memory 3 to be consists of two distinct areas: a first where the standard instructions are written and a second where the specific instructions are written.

L'appellation périphérique est donnée pour les systèmes de la montre qui sont utiles au fonctionnement de ladite montre et à la réalisation des fonctions que cette dernière propose. On peut citer par exemple comme périphérique toujours présent, le quartz accompagné de sa chaîne de division servant à cadencer les différents éléments. On peut d'ailleurs noter que le présent circuit 1 comprend un seul oscillateur pour cadencer tous les éléments de la montre. D'autres périphériques peuvent être les systèmes moteurs des aiguilles ou l'écran d'affichage selon qu'il s'agisse d'une montre analogique ou numérique. On peut également citer les entrées/sorties, c'est-à-dire les différents boutons de la montre, alors que des périphériques optionnels peuvent être les systèmes moteurs d'un chronographe ou les systèmes de gestion d'une quelconque fonction utilisant un capteur comme une boussole ou un altimètre ou autre.The peripheral designation is given for the systems of the watch which are useful for the operation of said watch and the realization of the functions that the latter proposes. For example, as a device always present, the quartz accompanied by its division chain for timing the different elements. It can also be noted that the present circuit 1 comprises a single oscillator for clocking all the elements of the watch. Other devices may be the motor systems of the hands or the display screen depending on whether it is an analog watch or digital. It is also possible to mention the inputs / outputs, that is to say the different buttons of the watch, while optional peripherals can be the engine systems of a chronograph or the management systems of any function using a sensor like a compass or altimeter or whatever.

Chaque périphérique est donc relié à un contrôleur de périphérique 4 situé dans ledit circuit électronique de montre 1. Ces contrôleurs comprennent chacun un registre d'initialisation 5 permettant de régler certaines données internes à chaque périphérique tel que par exemple les caractéristiques des impulsions motrices : fréquence, longueur ou autres dans le cas du contrôleur de périphérique du générateur d'impulsions motrices.Each device is thus connected to a peripheral controller 4 located in said electronic watch circuit 1. These controllers each include an initialization register 5 for setting certain internal data to each peripheral such as, for example, the characteristics of the driving pulses: frequency , length or other in the case of the device controller of the driving pulse generator.

Comme l'on peut le voir sur la figure 1, les différents éléments du circuit électronique 1 sont reliés entre eux via les moyens de liaison 6a, 6b et 7. Ces derniers sont représentés en sur la figure 1 en partie par 2 multiplexeurs 6a et 6b. Ces multiplexeurs 6a et 6b sont appelés multiplexeur d'initialisation 6a pour celui qui sert avant tout à permettre l'initialisation des registres d'initialisation 5 des contrôleurs de périphériques 4, et multiplexeur de fonctionnement 6b, pour celui qui sert quant à lui à permettre la circulation des données entre les différents éléments lorsque le circuit 1 est en fonctionnement normal.As can be seen on the figure 1 , the different elements of the electronic circuit 1 are connected to each other via the connecting means 6a, 6b and 7. These are represented on the figure 1 partly by 2 multiplexers 6a and 6b. These multiplexers 6a and 6b are called initialization multiplexer 6a for the one which serves above all to allow initialization of the initialization registers 5 of the peripheral controllers 4, and the operating multiplexer 6b, for the one which serves for its part. allow the flow of data between the different elements when the circuit 1 is in normal operation.

Les deux multiplexeurs 6a et 6b sont reliés aux différents éléments par des bus de communication 7. Parmi les éléments reliés ensemble via les multiplexeurs 6a et 6b et les bus de communication 7, on trouve le processeur 2 qui lui aussi est capable de communiquer avec les contrôleurs de périphériques 4. Ceci est dû au fait que le circuit 1 peut au choix être indépendant ou non vis-à-vis du processeur 2 et de la mémoire non volatile 3. On signalera par ailleurs que d'autres moyens de liaison 6a, 6b et 7 peuvent être utilisés dans le circuit électronique de montre 1 selon la présente invention.The two multiplexers 6a and 6b are connected to the different elements by communication buses 7. Among the elements connected together via the multiplexers 6a and 6b and the communication buses 7, there is the processor 2 which is also capable of communicating with the 4. This is because the circuit 1 may optionally be independent of processor 2 and nonvolatile memory 3. It will also be pointed out that other connection means 6a, 6b and 7 may be used in the electronic watch circuit 1 according to the present invention.

Comme souligné auparavant, le présent circuit 1 se distingue de ce qui est connu actuellement par la présence d'un moyen d'initialisation 8 permettant de configurer les contrôleurs de périphériques 4 et les moyens de liaison 6a, 6b et 7 c'est-à-dire les multiplexeurs 6a et 6b, afin que les périphériques puissent fonctionner en toute indépendance par rapport au processeur 2 et à la mémoire non volatile 3. Ce moyen d'initialisation 8 est représenté sur la figure 1 comme étant une mémoire programmable 8 contenant les données d'initialisation sensées être implantées dans les registres d'initialisation 5 des contrôleurs de périphériques 4 ainsi que les données d'initialisation des moyens de liaison 6a et 6b. Cette mémoire programmable 8 est reliée aux registres d'initialisation 5 des contrôleurs de périphériques 4 via le multiplexeur d'initialisation 6a et un bus de communication 7. Ce moyen d'initialisation 8, les contrôleurs de périphériques 4 et les moyens de liaison 6a, 6b et 7 forment l'ensemble autonome 9 servant à la montre pour fonctionner sans intervention du processeur 2 et de la mémoire non volatile 3.As noted above, the present circuit 1 differs from what is currently known by the presence of an initialization means 8 for configuring the peripheral controllers 4 and the connecting means 6a, 6b and 7 that is say the multiplexers 6a and 6b, so that the peripherals can operate completely independently of the processor 2 and the non-volatile memory 3. This initialization means 8 is represented on the figure 1 as a programmable memory 8 containing the initialization data to be implemented in the initialization registers 5 of the peripheral controllers 4 and the initialization data of the connecting means 6a and 6b. This programmable memory 8 is connected to the initialization registers 5 of the peripheral controllers 4 via the initialization multiplexer 6a and a communication bus 7. This initialization means 8, the peripheral controllers 4 and the connection means 6a, 6b and 7 form the autonomous assembly 9 used for the watch to operate without intervention of the processor 2 and the non-volatile memory 3.

Les instructions d'initialisation qui sont misent dans les registres d'initialisation 5 des contrôleurs de périphériques 4 sont les données suivantes. Comme données implantées dans les différents registres d'initialisation, on trouve tout d'abord les caractéristiques propres des périphériques comme celles citées auparavant, celles-ci ne concourant pas à la diminution de la consommation électrique du circuit 1, c'est-à-dire ne concourant pas à rendre les périphériques autonomes. La résolution du problème est effectuée par l'implantation d'instructions configurant les entrées / sorties de chaque contrôleur de périphérique 4.The initialization instructions that are set in the boot registers 5 of the peripheral controllers 4 are the following data. As data implanted in the various initialization registers, we first find the specific characteristics of the devices such as those mentioned before, these not contributing to the decrease in the power consumption of circuit 1, that is to say, not contributing to make the peripherals autonomous. The problem is solved by the implementation of instructions configuring the inputs / outputs of each device controller 4.

En effet, chaque contrôleur de périphérique 4 possède une série d'entrées / sorties lui permettant d'une part de communiquer avec le périphérique qui lui correspond, c'est-à-dire de réceptionner des informations provenant de ce dernier et d'autre part permettant de communiquer avec le processeur 2, c'est-à-dire de transmettre des informations au processeur 2 et de réceptionner les données de ce dernier qui seront à transmettre au périphérique. Or ce qui vient d'être décrit juste avant correspond à ce qu'il se passe dans un circuit selon l'art antérieur. En effet, c'est l'exemple du cas où l'on enclenche le chronographe par appui d'un bouton. Dans cet exemple, l'appui sur le bouton va engendrer un changement d'état de la variable correspondante, ce changement d'état va ensuite être transmit au processeur 2 via le contrôleur de périphérique 4 qui gère les différents boutons. A la suite de cela, le processeur 2 va traiter cette information c'est-à-dire interpréter ce que veut dire ce changement d'état et agir en conséquence, c'est-à-dire exécuter l'instruction qui gère le chronographe et la transmettre vers les périphériques correspondants à savoir les aiguilles et moteur du chronographe ainsi que de l'horloge.Indeed, each device controller 4 has a series of inputs / outputs allowing it on the one hand to communicate with the device that corresponds to it, that is to say to receive information from the latter and other part to communicate with the processor 2, that is to say to transmit information to the processor 2 and to receive the data of the latter to be transmitted to the device. But what has just been described just before corresponds to what happens in a circuit according to the prior art. Indeed, this is the example of the case where you engage the chronograph by pressing a button. In this example, pressing the button will generate a change of state of the corresponding variable, this change of state will then be transmitted to the processor 2 via the device controller 4 which manages the different buttons. Following this, the processor 2 will process this information, that is to say, interpret what this change of state means and act accordingly, that is to say execute the instruction that manages the chronograph and transmit it to the corresponding peripherals, namely the chronograph and chronograph hands and motor as well as the clock.

Or la présente invention diffère de l'art antérieur en ce que, dans le cas de l'exemple ci-dessus, le changement d'état de la variable du bouton actionné va être directement envoyé aux périphériques afin que ceux-ci puissent remplir leur fonction. Ainsi, on se débarrasse d'un transfert et d'un traitement des informations par le processeur 2 qui d'une part, nous permet de gagner du temps de cycles et d'autre part, nous permet de gagner en consommation puisqu'il n'est nul besoin de mettre en fonction le processeur 2 afin d'effectuer ces tâches.However, the present invention differs from the prior art in that, in the case of the example above, the change of state of the actuated button variable will be sent directly to the peripherals so that they can fulfill their purpose. function. Thus, we get rid of a transfer and processing of information by the processor 2 which on the one hand, allows us to save time of cycles and on the other hand, allows us to gain in consumption since n There is no need to turn on processor 2 to perform these tasks.

De ce fait, un procédé pour la mise en route du circuit électronique de montre 1 et plus généralement de la montre a été mis au point. Effectivement, au démarrage, tous les systèmes sont normalement éteints, ainsi l'initialisation des registres d'initialisation 5 des contrôleurs de périphériques 4 ne peut être effectuée. Ainsi, il est prévu dans le circuit électronique 1 de la présente invention de mettre un contrôleur de gestion chargé en outre du démarrage du circuit 1. Pour cela, le contrôleur de gestion présenté ci-dessus va accéder à la mémoire programmable 8 contenant les données d'initialisation, lire ces données pour enfin transférer ces données vers les registres d'initialisation 5 des contrôleurs de périphériques 4 leur étant destinées. Une fois, ce procédé terminé, la montre se met en fonctionnement.As a result, a method for starting the electronic watch circuit 1 and more generally the watch has been developed. Indeed, at start-up, all systems are normally off, so initialization of the boot registers 5 of the peripheral controllers 4 can not be performed. Thus, it is provided in the electronic circuit 1 of the present invention to put a management controller further responsible for starting the circuit 1. For this, the management controller presented above will access the programmable memory 8 containing the data. initialization, read this data to finally transfer this data to the initialization registers 5 of the device controllers 4 intended for them. Once this process is complete, the watch goes into operation.

Néanmoins, il est à signaler que ce n'est pas forcément le contrôleur de gestion qui ordonne l'initialisation des registres 5 des contrôleurs de périphériques 4. Ainsi, cette lecture de la mémoire programmable 8 et les opérations qui s'en suivent peuvent être effectuées automatiquement à la mise sous tension. Une autre solution consiste à définir dans la mémoire un bit dont la valeur permet soit une initialisation automatique, soit une initialisation par le contrôleur de gestion.Nevertheless, it should be noted that it is not necessarily the management controller that orders the initialization of the registers 5 of the peripheral controllers 4. Thus, this reading of the programmable memory 8 and the operations that follow can be performed automatically when the power is turned on. Another solution is to define in the memory a bit whose value allows either an automatic initialization or an initialization by the management controller.

Il a été dit précédemment que le circuit électronique de montre 1 avait la possibilité d'utiliser le processeur 2 afin d'exécuter des instructions spécifiques. Mais il est à signaler que le processeur 2 peut également être mis en fonction pour exécuter des instructions standards si cela est nécessaire. C'est pourquoi, nous allons expliquer ci-après le procédé afin que le processeur 2 soit utilisé dans le but d'exécuter ces instructions.It has been said previously that the electronic watch circuit 1 had the possibility of using the processor 2 in order to execute specific instructions. But it should be noted that the processor 2 can also be turned on to execute standard instructions if necessary. Therefore, we will explain below the process so that the processor 2 is used for the purpose of executing these instructions.

En effet, le processeur 2 doit pouvoir être remis à tout moment en fonction dès lors qu'une instruction qu'elle soit spécifique ou standard, doit être exécutée par ledit processeur 2. Pour cela, il est prévu que chaque périphérique puisse être capable d'envoyer un signal d'interruption via les moyens de liaison 6a, 6b et 7 jusqu'au processeur 2. Ce signal d'interruption permet la mise en fonctionnement du processeur 2 afin d'exécuter les instructions stockées dans la mémoire non volatile 3. Pour ce faire, le signal d'interruption, une fois réceptionné par le processeur 2, va enclencher le réveil de ce dernier, qui va alors passer d'un mode passif à un mode actif où il pourra exécuter des tâches. Ainsi le processeur 2 va accéder à la mémoire non volatile, lire l'instruction correspondante puis l'exécuter, une fois cette instruction exécutée, le processeur 2 va pouvoir passer d'un mode actif à un mode passif afin de se mettre en veille pour réduire la consommation électrique globale du circuit électronique de montre 1. Préférentiellement, ce mode d'exécution, où un signal d'interruption sert à permettre l'exécution d'instructions par le processeur 2, est utilisé pour l'exécution des instructions spécifiques.Indeed, the processor 2 must be able to be reset at any time as soon as an instruction that it is specific or standard, must be executed by said processor 2. For this, it is expected that each device can be able to send an interruption signal via the connection means 6a, 6b and 7 to the processor 2. This interrupt signal enables the operation of the processor 2 so that to execute the instructions stored in the nonvolatile memory 3. To do this, the interrupt signal, once received by the processor 2, will trigger the awakening of the latter, which will then go from a passive mode to a active mode where he can perform tasks. Thus the processor 2 will access the non-volatile memory, read the corresponding instruction and then execute it, once this instruction has been executed, the processor 2 will be able to switch from an active mode to a passive mode in order to reduce the overall power consumption of the electronic watch circuit 1. Preferably, this embodiment, where an interruption signal is used to allow the execution of instructions by the processor 2, is used for the execution of specific instructions.

On comprendra que diverses modifications et/ou améliorations et/ou combinaisons évidentes pour l'homme du métier peuvent être apportées aux différents modes de réalisation de l'invention exposé ci-dessus sans sortir du cadre de l'invention défini par les revendications annexées.It will be understood that various modifications and / or improvements and / or combinations obvious to those skilled in the art can be made to the various embodiments of the invention set forth above without departing from the scope of the invention defined by the appended claims.

Claims (12)

Circuit électronique pour la gestion du fonctionnement d'une montre (1), ledit circuit comprenant un processeur (2) relié à une mémoire non volatile (3), qui contient des instructions à réaliser, des contrôleurs de périphériques (4) pour interagir avec des périphériques de la montre, et des moyens de liaison (6a, 6b et 7) agencés pour permettre aux contrôleurs de périphériques, à la mémoire non volatile et au processeur de communiquer des informations relatives au fonctionnement de ladite montre les uns avec les autres, caractérisé en ce que ledit circuit électronique de montre comprend en outre un moyen d'initialisation (8) susceptible d'agir sur les contrôleurs de périphériques pour les initialiser en leur envoyant des données sans intervention du processeur (2) et leur permettre d'exécuter des opérations indépendamment du processeur et/ou de la mémoire non volatile.An electronic circuit for managing the operation of a watch (1), said circuit comprising a processor (2) connected to a non-volatile memory (3), which contains instructions to be made, peripheral controllers (4) for interacting with watch peripherals, and link means (6a, 6b and 7) arranged to enable the peripheral controllers, the nonvolatile memory and the processor to communicate information relating to the operation of said watch with each other, characterized in that said watch electronic circuit further comprises an initialization means (8) capable of acting on the peripheral controllers to initialize them by sending them data without intervention of the processor (2) and enabling them to execute operations independently of the processor and / or the non-volatile memory. Circuit électronique selon la revendication 1, caractérisé en ce que le moyen d'initialisation (8) est une mémoire programmable (8) dans laquelle sont mémorisées des données de configuration des contrôleurs de périphériques (4) afin de pouvoir réaliser l'initialisation desdits contrôleurs en fonction de caractéristiques propres à chaque périphérique et/ou des entrées/sorties de chaque contrôleur de périphérique avec les autres éléments du circuit électronique (1).Electronic circuit according to claim 1, characterized in that the initialization means (8) is a programmable memory (8) in which configuration data of the peripheral controllers (4) are stored in order to be able to initialize said controllers. according to characteristics specific to each device and / or the inputs / outputs of each device controller with the other elements of the electronic circuit (1). Circuit électronique selon la revendication 2, caractérisé en ce que la configuration des contrôleurs de périphériques (4) est ordonnée par un contrôleur de gestion.Electronic circuit according to claim 2, characterized in that the configuration of the peripheral controllers (4) is ordered by a management controller. Circuit électronique selon la revendication 2, caractérisé en ce que la configuration des contrôleurs de périphériques (4) est susceptible d'être effectuée automatiquement au démarrage du circuit électronique (1).Electronic circuit according to claim 2, characterized in that the configuration of the peripheral controllers (4) is capable of being performed automatically at the start of the electronic circuit (1). Circuit électronique selon la revendication 2, caractérisé en ce que la configuration des contrôleurs de périphériques (4) est commandée en fonction de la valeur d'un bit écrit dans ladite mémoire programmable (8).Electronic circuit according to Claim 2, characterized in that the configuration of the peripheral controllers (4) is controlled according to the value of a bit written in said programmable memory (8). Circuit électronique selon l'une des revendications 1 à 5, caractérisé en ce que les moyens de liaison (6a, 6b et 7) comprennent au moins un bus de communication (7) et au moins un multiplexeur (6a, 6b) configuré par des données du moyen d'initialisation (8) et agencé pour gérer les communications des différents éléments du circuit électronique (1) les uns avec les autres.Electronic circuit according to one of claims 1 to 5, characterized in that the connecting means (6a, 6b and 7) comprise at least one communication bus (7) and at least one multiplexer (6a, 6b) configured by means of data of the initialization means (8) and arranged to manage the communications of the different elements of the electronic circuit (1) with each other. Circuit électronique selon l'une des revendications 1 à 6, caractérisé en ce que le processeur (2) est susceptible de passer d'un mode passif à un mode actif dans lequel il peut exécuter des instructions suite à la génération d'une interruption provenant d'un périphérique.Electronic circuit according to one of claims 1 to 6, characterized in that the processor (2) is able to switch from a passive mode to an active mode in which it can execute instructions following the generation of an interrupt from a device. Circuit électronique selon la revendication 7, caractérisé en ce que lors de la génération d'une interruption, la mémoire non volatile (3) passe également d'un mode passif à un mode actif pour communiquer avec le processeur (2).Electronic circuit according to claim 7, characterized in that during the generation of an interrupt, the non-volatile memory (3) also switches from a passive mode to an active mode for communicating with the processor (2). Circuit électronique selon l'une des revendications 1 à 8, caractérisé en ce que la mémoire non volatile (3) est répartie en deux zones, une première zone pour contenir des lignes de codes d'applications standards et une seconde zone pour contenir des lignes de codes d'applications spécifiques.Electronic circuit according to one of Claims 1 to 8, characterized in that the non-volatile memory (3) is divided into two zones, a first zone for holding standard application code lines and a second zone for containing lines. specific application codes. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce qu'un unique oscillateur est utilisé pour cadencer tous les éléments du circuit (1).Electronic circuit according to one of the preceding claims, characterized in that a single oscillator is used to clock all the elements of the circuit (1). Procédé de mise en action d'un circuit électronique de montre (1) selon l'une des revendications précédentes, caractérisé en ce qu'il comprend, au démarrage, les étapes : - d'accéder au moyen d'initialisation (8), - de lire des données mémorisées dans le moyen d'initialisation (8), - d'exécuter des instructions de configuration mémorisées dans le moyen d'initialisation. Method for actuating an electronic watch circuit (1) according to one of the preceding claims, characterized in that it comprises, at startup, the steps: to access the initialization means (8), to read data stored in the initialization means (8), to execute configuration instructions stored in the initialization means. Procédé selon la revendication 11, caractérisé en ce que lorsque le processeur (2) passe d'un mode passif à un mode actif où il peut exécuter des instructions, le procédé comprend les étapes de: - recevoir un signal d'interruption d'au moins un périphérique de la montre, ce signal étant transmis au processeur via les moyens de liaison (6a, 6b et 7), - mettre en fonction le processeur (2), - exécuter l'instruction correspondant au signal d'interruption, par le processeur (2), et - mettre dans le mode passif le processeur (2) au terme de l'exécution de l'instruction. Method according to claim 11, characterized in that when the processor (2) switches from a passive mode to an active mode where it can execute instructions, the method comprises the steps of: receiving an interrupt signal from at least one device of the watch, this signal being transmitted to the processor via the connecting means (6a, 6b and 7), - turn on the processor (2), executing the instruction corresponding to the interrupt signal, by the processor (2), and - Put in the passive mode the processor (2) at the end of the execution of the instruction.
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2977690B1 (en) * 2011-07-04 2013-08-02 St Microelectronics Rousset METHOD FOR INITIALIZING PERIPHERAL ORGAN REGISTERS IN A MICROCONTROLLER
US9002322B2 (en) 2011-09-29 2015-04-07 Apple Inc. Authentication with secondary approver
US8769624B2 (en) 2011-09-29 2014-07-01 Apple Inc. Access control utilizing indirect authentication
WO2014143776A2 (en) 2013-03-15 2014-09-18 Bodhi Technology Ventures Llc Providing remote interactions with host device using a wireless device
US9483763B2 (en) 2014-05-29 2016-11-01 Apple Inc. User interface for payments
US11256294B2 (en) 2014-05-30 2022-02-22 Apple Inc. Continuity of applications across devices
US9967401B2 (en) 2014-05-30 2018-05-08 Apple Inc. User interface for phone call routing among devices
US10339293B2 (en) 2014-08-15 2019-07-02 Apple Inc. Authenticated device used to unlock another device
WO2016128578A1 (en) * 2015-02-13 2016-08-18 Microdul Ag Electronic circuit for controlling the operation of a watch
DK179186B1 (en) 2016-05-19 2018-01-15 Apple Inc REMOTE AUTHORIZATION TO CONTINUE WITH AN ACTION
US10621581B2 (en) 2016-06-11 2020-04-14 Apple Inc. User interface for transactions
WO2017218094A1 (en) * 2016-06-12 2017-12-21 Apple Inc. User interfaces for transactions
DK201670622A1 (en) 2016-06-12 2018-02-12 Apple Inc User interfaces for transactions
US9842330B1 (en) 2016-09-06 2017-12-12 Apple Inc. User interfaces for stored-value accounts
US10496808B2 (en) 2016-10-25 2019-12-03 Apple Inc. User interface for managing access to credentials for use in an operation
US10992795B2 (en) 2017-05-16 2021-04-27 Apple Inc. Methods and interfaces for home media control
US11431836B2 (en) 2017-05-02 2022-08-30 Apple Inc. Methods and interfaces for initiating media playback
CN111343060B (en) 2017-05-16 2022-02-11 苹果公司 Method and interface for home media control
US20220279063A1 (en) 2017-05-16 2022-09-01 Apple Inc. Methods and interfaces for home media control
KR102185854B1 (en) 2017-09-09 2020-12-02 애플 인크. Implementation of biometric authentication
KR102143148B1 (en) 2017-09-09 2020-08-10 애플 인크. Implementation of biometric authentication
US11170085B2 (en) 2018-06-03 2021-11-09 Apple Inc. Implementation of biometric authentication
CN113748408A (en) 2019-05-31 2021-12-03 苹果公司 User interface for audio media controls
US11010121B2 (en) 2019-05-31 2021-05-18 Apple Inc. User interfaces for audio media control
US11816194B2 (en) 2020-06-21 2023-11-14 Apple Inc. User interfaces for managing secure operations
US11392291B2 (en) 2020-09-25 2022-07-19 Apple Inc. Methods and interfaces for media control with dynamic feedback
US11847378B2 (en) 2021-06-06 2023-12-19 Apple Inc. User interfaces for audio routing
US11784956B2 (en) 2021-09-20 2023-10-10 Apple Inc. Requests to add assets to an asset account

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04316114A (en) * 1991-04-16 1992-11-06 Seiko Epson Corp Cpu ic for clock
US5289452A (en) * 1988-06-17 1994-02-22 Seiko Epson Corporation Multifunction electronic analog timepiece
US7072080B1 (en) * 1999-09-02 2006-07-04 Brother Kogyo Kabushiki Kaisha Information processor
US20060285442A1 (en) * 2005-03-25 2006-12-21 Jean-Bernard Maeder Timepiece having compass feature

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5169664A (en) * 1974-12-13 1976-06-16 Suwa Seikosha Kk Denshidokei
US4219999A (en) * 1977-03-03 1980-09-02 Citizen Watch Company, Limited Electronic timepiece equipped with battery life display
JPS59200327A (en) * 1983-04-26 1984-11-13 Nec Corp Control system of peripheral device
JPS6188179A (en) * 1984-10-05 1986-05-06 Seiko Instr & Electronics Ltd Display of life of battery in electronic time piece
US5633573A (en) * 1994-11-10 1997-05-27 Duracell, Inc. Battery pack having a processor controlled battery operating system
JP3062253B2 (en) * 1996-08-01 2000-07-10 シチズン時計株式会社 Electronic clock
US5995820A (en) * 1997-06-17 1999-11-30 Lsi Logic Corporation Apparatus and method for calibration of sleep mode clock in wireless communications mobile station
JP3816197B2 (en) * 1997-07-18 2006-08-30 シチズン時計株式会社 Rechargeable electronic watch
JP4481497B2 (en) * 1998-08-31 2010-06-16 シチズンホールディングス株式会社 Electronic watch with power generation function
JP4560158B2 (en) * 1999-11-24 2010-10-13 シチズンホールディングス株式会社 Rechargeable electronic watch
JP4316114B2 (en) 2000-06-30 2009-08-19 コニカミノルタホールディングス株式会社 Model deformation method and modeling apparatus
JP5025070B2 (en) * 2000-09-27 2012-09-12 シチズンホールディングス株式会社 Electronic clock
JP3905703B2 (en) * 2000-11-29 2007-04-18 株式会社ルネサステクノロジ Data processor and data processing system
US6961859B2 (en) * 2002-01-30 2005-11-01 Hewlett Packard Development Company, L.P Computing device having programmable state transitions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289452A (en) * 1988-06-17 1994-02-22 Seiko Epson Corporation Multifunction electronic analog timepiece
JPH04316114A (en) * 1991-04-16 1992-11-06 Seiko Epson Corp Cpu ic for clock
US7072080B1 (en) * 1999-09-02 2006-07-04 Brother Kogyo Kabushiki Kaisha Information processor
US20060285442A1 (en) * 2005-03-25 2006-12-21 Jean-Bernard Maeder Timepiece having compass feature

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US8130596B2 (en) 2012-03-06
EP2063328A3 (en) 2010-03-03
EP2063328B1 (en) 2019-04-24
EP2063327A1 (en) 2009-05-27
US20090135678A1 (en) 2009-05-28

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